Delay cells are generally employed in delay locked loops (DLLs) and duty cycle corrector (DCC) circuits. In operation, a control voltage can be applied to the delay cell to vary the length of the delay through the cell. Some examples of conventional delay cells can be seen in FIGS. 1 and 2.
Turning to FIG. 1 of the drawings, the reference numeral 100 generally designates a conventional load based delay cell. The delay cell 100 is generally comprised of PMOS transistor Q1, NMOS transistors Q2 and Q3, capacitor-connected NMOS transistor Q4, and capacitor C1. Capacitor-connected NMOS transistor Q4 and capacitor C1 have capacitances of bout 0.6 pF and 12 fF, respectively. Transistors Q1 and Q2 are configured as an inverter with transistor Q3 coupled to the output terminal of the inverter. A control voltage CNTL can be applied to the gate of transistor Q3 so that the delay of cell 100 can be varied.
Turning to FIG. 2 of the drawings, the reference numeral 200 generally designated a conventional current starved delay cell. Delay cell 200 replaces transistors Q3 and Q4 of cell 100 with transistors Q5 and Q6 (which are NMOS transistors coupled in series between the source of transistor Q2 and supply rail VSS. With cell 200, a control voltage CNTL is applied to the gates of transistors Q5 and Q6 so that the delay of cell 200.
A typical application for cells 100 and 200 may specify support for more than 10× variation in clock frequencies. To support such a wide locking range, the delay cell 100 or 200 would generally support wide delay ranges. Cells 100 and 200, though, do not have such a wide delay range. Several different solutions exist that employ these cells, but each of those designs have drawbacks.